Source: nextpnr
Maintainer: Debian Electronics Team <pkg-electronics-devel@lists.alioth.debian.org>
Uploaders: Ruben Undheim <ruben.undheim@gmail.com>,
           Nathaniel Graff <nathaniel.graff@sifive.com>,
           Daniel Gröber <dxld@darkboxed.org>
Section: electronics
Priority: optional
Build-Depends: debhelper-compat (= 13),
               cmake,
               qtbase5-dev,
               libboost-filesystem-dev,
               libboost-thread-dev,
               libboost-program-options-dev,
               libboost-python-dev,
               libboost-iostreams-dev,
               libqt5opengl5-dev,
               libeigen3-dev,
               python3-dev,
               fpga-icestorm-chipdb (>= 0~20180809git7e73288-2),
               help2man
Standards-Version: 4.6.1
Vcs-Browser: https://salsa.debian.org/electronics-team/nextpnr
Vcs-Git: https://salsa.debian.org/electronics-team/nextpnr.git
Homepage: https://github.com/YosysHQ/nextpnr
Rules-Requires-Root: no

Package: nextpnr-ice40
Architecture: any
Depends: ${shlibs:Depends},
         ${misc:Depends}
Suggests: yosys, fpga-icestorm
Conflicts: nextpnr-ice40-qt
Replaces: nextpnr-ice40-qt
Description: FPGA place and route tool for Lattice iCE40
 FPGA are computer chips that have parts of their logics dependent on
 parameters that can be set after production, i.e., that can be programmed.
 To map a problem to an FPGA, a program must first be broken down to a
 series of logic elements and their connections, which is performed by
 a compiler like yosys. Downstream from there nextpnr takes over and decides
 what exact logic cell should be used that is on the chip.
 .
 nextpnr is a FPGA place and route tool, taking an FPGA model specific
 topological description of the hardware to be realised and produces a
 gate-level description with logic and it's connections mapped onto onto
 specific hardwired functional units using a propagation timing-based
 algorithm. Analysing the fully implemented design for proper operation at
 speed is also supported using timing-analysis.
 .
 nextpnr-ice40 supports the Lattice iCE40 series of FPGAs and uses the
 hardware description chipdb from the fpga-icestorm package.
 .
 This package supports only the command-line interface, there is also a GUI
 version in the nextpnr-ice40-qt package.

Package: nextpnr-ice40-qt
Architecture: any
Depends: ${shlibs:Depends},
         ${misc:Depends}
Suggests: yosys, fpga-icestorm
Conflicts: nextpnr-ice40
Replaces: nextpnr-ice40
Description: FPGA place and route tool for Lattice iCE40 - with GUI
 FPGA are computer chips that have parts of their logics dependent on
 parameters that can be set after production, i.e., that can be programmed.
 To map a problem to an FPGA, a program must first be broken down to a
 series of logic elements and their connections, which is performed by
 a compiler like yosys. Downstream from there nextpnr takes over and decides
 what exact logic cell should be used that is on the chip.
 .
 nextpnr is a FPGA place and route tool, taking an FPGA model specific
 topological description of the hardware to be realised and produces a
 gate-level description with logic and it's connections mapped onto onto
 specific hardwired functional units using a propagation timing-based
 algorithm. Analysing the fully implemented design for proper operation at
 speed is also supported using timing-analysis.
 .
 nextpnr-ice40 supports the Lattice iCE40 series of FPGAs and uses the
 hardware description chipdb from the fpga-icestorm package.
 .
 This package supports both the GUI and command-line interfaces. A slimmer
 command-line only version is available in the nextpnr-ice40 package.

Package: nextpnr-generic
Architecture: any
Depends: ${shlibs:Depends},
         ${misc:Depends}
Description: Place and route tool for Generic FPGAs
 FPGA are computer chips that have parts of their logics dependent on
 parameters that can be set after production, i.e., that can be programmed.
 To map a problem to an FPGA, a program must first be broken down to a
 series of logic elements and their connections, which is performed by
 a compiler like yosys. Downstream from there nextpnr takes over and decides
 what exact logic cell should be used that is on the chip.
 .
 nextpnr is a FPGA place and route tool, taking an FPGA model specific
 topological description of the hardware to be realised and produces a
 gate-level description with logic and it's connections mapped onto onto
 specific hardwired functional units using a propagation timing-based
 algorithm. Analysing the fully implemented design for proper operation at
 speed is also supported using timing-analysis.
 .
 nextpnr-generic supports nextpnr's synthetic "generic" FPGA.
